1. Technical Field
The present invention relates to memory management in a processing system and, more particularly, to a processing system implementing variable page size memory organization using a multiple page per entry translation lookaside buffer.
2. Related Art
There are a variety of different manners in which the memory of a processing system may be organized. One such manner is through the use of virtual memory. Virtual memory allows software to run in a memory address space in which the size and addressing of the memory space is not tied strictly to the physical memory of the processing system. In virtual memory systems, the operating system maps virtual memory to physical memory. The operating system uses this mapping to detect when an address is required that does not currently relate to main memory so that the requested data can be accessed.
Virtual memory may be implemented through paging. When the processing system uses paging, the low order bits of the virtual address are preserved and used directly as the low order bits of the actual physical address. In contrast, the high order bits may be treated as a key or index to one or more address translation tables that correspond to a range of consecutive physical addresses. The memory referenced by such a range may be called a page. Page sizes may range in size, for example, from 512 bytes through 8 megabytes.
The mappings between virtual memory and physical memory may be stored in page table entries of a page table array. These page table entries may be used by the operating system to execute and virtual address to physical address translations. The processing system also may include a translation lookaside buffer (TLB) to enhance the efficiency with which virtual memory addresses are translated to the corresponding physical addresses. The TLB is a cache that may have a fixed number of entries containing parts of various page table entries to improve the speed of the translation of a virtual address to its corresponding physical address. A TLB may include a content-addressable memory in which the search key is the virtual address and the search result is the physical address and access permissions. If the search of the TLB yields a match, the translation is known very quickly, and the physical address is used to access memory. If the virtual address is not in the TLB, the translation proceeds via the page table, which may take longer to complete.
The page size of the virtual/physical address space often may be fixed and/or difficult to dynamically change. Nevertheless, the page size(s) used in the page table entries and the TLB entries may have an impact on the performance of the system memory. Smaller page sizes may be advantageous when high granularity control of the memory access permissions is required. Likewise, small page sizes may be advantageous when applications only require small portions of the virtual memory space for their operation. Large page sizes, however, may be advantageous when used in connection with a TLB since TLB misses are less likely to occur when the virtual memory space is organized into large pages.
Many systems that employ multiple page sizes do so in a static manner. The versatility of such systems may be very limited. Other systems implement multiple page sizes in a dynamic manner using hardware. Multiple TLBs also may be used with different characteristics associated with each page size. However, the manner in which the multiple page sizes may be realized is restricted to the manner in which it is implemented in the hardware and can add a significant amount of cost to the system.
The difficulty of managing multiple page sizes is also present in systems that employ a MIPS-like architecture. The TLB in a MIPS-like architecture associates multiple physical pages with each TLB entry and may be difficult to manage efficiently. Therefore, a need exists for an improved system that can implement variable page sizes using a multiple page per entry translation lookaside buffer.